Ulysses-ESC_1.0 Project Log¶

By gugan73715 · Last updated: September 16, 2026 · Created: September 14, 2026

DATE: August 9, 2026¶

Finally understood why 3 phase is more effecient fundamentally, and finally able to feel it make it sense. (Kind of had a idea before but could not feel it)

DATE: August 10, 2026¶

Learnt about stator, rotor, mag fields in a motor, rotation mag field, constant power, math behind V/I/P in a motor, 90 deg between stator and rotor field etc.. (Cleared up some really stupid misunderstandings)
Cleared up doubts about back emf, how it is used for six step commutation / FOC and RPM, typical back emf plot, zero crossing, relation to flux, how phase currents are used for FOC etc..
Looked into high level of a typical ESC, design considerations like Dead time, shoot through, thermal, PWM freq considerations, parasitics etc.
FOC vs Six step trapeziodal, wanted to do FOC cause sounds cooler but it would be stupidly overkill with no benefit so decided on Six Step Commutation
Cleared up some really stupid doubts and mistakes (Took a while to get there)
Added all the good papers from silicon manufactures on all the topic's above that i used for research to the reference resources folder
Looked into AM32, compatible hardware options, opensource projects, constraints etc..
Specced out a FET - Infineon IAUC120N04S6L005ATMA1, wowed by this FET, just amazing. Extreamely low RDS(on) - 0.43mR @ VGS >= 10V, \(\theta\)-ja of just 27, did thermal calc - temp rise of about 18 C only at 40A: Do not need a heatsink (Yay). Some stock in LCSC and little expensive but worth it
Decided on STM32G071C8T6 MCU, AM32 compatibile, M0+ Arm Cortex, 128Kb flash, 32Kb RAM, 64MHz, LQFP 48 and just 2 Bucks plus good stock in LCSC. Should be good
Decided on shunt based current monitoring for each phase and for battery
Looked into TVS Diodes and Decoupling caps at Vbat and phase out to handle proper decoupling, dv/dt spikes, inductive kickback (L*di/dt), back-emf and phase voltage adding/subracting, speccing for worst case, FET VDSmax global limit, regenerative braking - charging the lipo with it, braking circuit, braking strength, back emf adding in braking phase and subracting in drive phases
Decided on low ESR/ESL decoupling cap network (probably low ESR polymer tantalum - KEMET) at Vbat phase inputs for local reservoir, smooth out the ripple / spikes and enable fast switching, TVS at Vbat phase input for ESD to protect lipo/FET VDSmax from voltage spikes and TVS at phase output for ESD and extra clamping
Combining the above with low braking strength(Reduce Duty cycle slowly) - set in AM32 firmware to reduce parasitics and keep the regen. current low and Important to spec TVS and Caps to Vphase + Back-emf + overshoot (worst case)
Clarified Dead time control vs Shoot through protection vs interlock, aiming for Dynamic dead-time control plus shoot through protection (Miller clamp or Strong pull down) to handle dv/dt FET turning on or interlock feature

Summary :

Deepdive on ESC fundamentals and developed decent understanding of it
Finalized high level architechture such as Six step vs FOC etc..
Specced out the main components
Deepdive into portection and parasitcs handling circuits

DATE: August 11, 2026¶

Revision of everything learnt yesterday especially question i had, mistakes i made, misunderstandings etc..
Looked into freewheeling and using FET's body diode to freewheel Inductive kick back (very intresting) how opposite FET body diode forward biases, how it happens during dead time, timeline of events etc...

DATE: August 12, 2026¶

Cleared up little cofusion about bootstrap cap, how it sits between BST and SW node - charged to 12V/Driver Voltage when low and VCC + 12V when SW node is high and that BST is connected to high side fet gate to keep it on
Found some repos on open source ESC designs and just messing around for reference
Started search for gate driver IC, looked through Infineon, TI, Analog Devices and some other company products and factoring in LCSC price and stock, finalized either a DRV series IC (TI) or two infineon IC options.

DATE: August 13, 2026¶

Decided on DRV8353SRTAR Gate Driver cause well know chip series, Has all the specs needed, cheap and good stock in LCSC and TI's smart gate architechture makes design easier.
Added Footprints for FET and MCU in our altium library

DATE: August 15, 2026¶

Added Footprint for Gate Driver in our altium library

DATE: August 16, 2026¶

Looked into how to spec switching frequency for PWM and target rise and fall time, learnt that higher freq. / lower rise time means smoother drive but more switching losses and vice-versa. General ESC PWM freqency is between 25-96 KHz, with 48 KHz being generally used value. Thinking of just using 48 KHz, and looking into rise and fall time calculation, need to learn a few things first.
Thinking about the high level of battery monitoring / balancing, mainly which circuit should be in ESC board and which in Backplane cause anything carrying current related to battery preferred to have it on ESC board to keep current loop small but if on Backplane, then that funcionality can be used without ESC board.

DATE: August 20, 2026¶

Still stuck on where to put the balancing circuit and charger circuit. Looking into switching to different connector with high current rating so can run balance current and charging current using multiple pins in parallel
Looked through like 1000 connectors across samtech, molex, TE, LCSC. Only found one in TE that might work but out of stock. Considering order now itself and will receive when in stock
Important: Need to account for return path of current as well. So a GND pin next to each balance and charge pin to force most current to return through these GND pins or else current will return on same pins as signal's. (Current takes the path of least resistance)

DATE: August 21, 2026¶

Clarified that one of the core jobs of the decoupling cap network in VBAT in to half bridge is to absorb Ldi/dt spike and inductive kick back (regn.) to protect the bus and TVS as final layer of protection to clamp any more spikes. Imporper sizing will blow the fets up
Switching to 294152-E / 5-104550-6 board to board connector cause it can handle 3.6A per pin but no stock in LCSC so i am going to get free samples from TE. Can run charging and balancing current through a few pins in parallel
Final Decision made: Battery charging and monitoring / balancing circuit goes in backplane, Only fuel gauge and current monitoring circuit with shunt in ESC and Fuel Gauge I2C to FC

DATE: August 24, 2026¶

Learnt about miller effect - the gate voltage plateaus when the FET turns on (Vgs above threshold voltage) which charges the gate - drain cap and gate current flows to charge this cap instead of Gate - Source cap which holds the gate voltage constant and once drain voltage settles at full drive voltage, garte voltage rises again.
Problem is when the high side FET hits miller plateau, the source voltage of high side FET (SW node) rises to full drive voltage which charges the gate - drain cap of low side FET and that current splits at gate cause of gate-source capacitance and gate resistor connected driver, the current flowing out of gate into gate resistor causes a voltage drop which rises the gate voltage of low side FET and if it crosses the threshold voltage, then low side FET will turn-on causing shoot-through and blowing the FET's up.
Solutions are strong pull down or active miller clamp (FET to GND). DRV8353SRTAR has inbuilt strong pull down to prevent this exact false turn on due to dv/dt. Yay

DATE: August 25, 2026¶

I am so stupid, i can just put the battery balance connector in the backplane itself, they are mounted vertically so they are next to each other. how did i not think of that. Just the charging current needs to go from Backplane to ESC. Decided.
Work around for out of stock TE connector, decided on using the 50 pin version which is in stock. Will order the samples soon
Important: Size the inter board digital buses keeping in mind that it runs through connectors and bus length is long so keep the bus capacitance under limits and use strong pull ups for lower rise time.
Started looking into overshoot and undershoot, causes, risks and how to handle it etc.. (Reminder that undershoot may be more fatal cause a chip's internal weak clamp / ESD diode would forward bias and blow itself up)

DATE: August 26, 2026¶

Saw some cool stuff at work, saw a full H-bridge PWM waveform with dead time, rise time, fall time, undershoot, overshoot, inductive kickback etc.. very cool

DATE: August 28, 2026¶

Revised again why 3 phase power is more efficient, not just for ESC but in general as well - constant instantaneous power leading smooth current so no ripple or overshoot losses is primary reason for higher efficiency. (Do not need return conductor helps as well)

DATE: September 11, 2026¶

Spent like a week breaking my head about FET thermal calculations, especially about using PCB as a heatsink, thermal vias, lateral spread etc..., for the USB-C PD Charger DFT PCB but applies very well here. Have a much better understanding now.
Quick summary: Two main elements to consider for Cu plane/pour, R_Surface to Ambient and R_lateral (very difficult to estimate), high density thermal vias on IC thermal pad/EP brings down R_vias and a pour on the EP does not help with lateral resistance but increases surface area which reduces R_SA. Also 2 oz Cu is expensive, so use pour on outer layers with thermal vias to achieve a good R_total. (Refer to USB-C PD Charger Logs / Docs for detailed notes)

DATE: September 12, 2026¶

Major Architectural Change: The USB-C PD Charger is going a serperate DFT PCB cause we have two lipo we can just swap and it seems overkill to put a charger in drone. Shadab also wants one of these for COTS so helps there as well. Main changes are no more charge current through connector problem so will finalize a different B to B connector soon.

DATE: September 13, 2026¶

Major Architectural Change: I am making a new FC (Yay) cause the PCIe is so annoying, very difficult to mount, we are not using half the stuff in there. I am going to desolder the MCU from old FC and solder it in new FC to save money and not refactor firmware again (Firmware and controls happy with it). So the stack is new FC, backplane and ESC now.
Major Architectural Change: Sensor board is merged with FC now so all the sensors in FC itself cause why have two boards with sensors on it, makes sense to combine, simplifies stack.
Major Logistics Change: I am hiring Ken for TVR Hardware, he seems pretty decent, i have seen him around in hennings regularly, he is commited and hannah seems to like him so ticks all the boxes for me. He will be taking over the backplane PCB and Test PCB.
I am adding a UART from ESC MCU to FC just so they can talk to each other incase needed.

DATE: September 15, 2026¶

Pin Assignment mostly done, decided on BB51-84AT-1-3HB 84 Pin, 1mm pitch, keyed, only about 1.5 CAD and decent stock in LCSC.
Dynamixel and Battery will plug into ESC PCB vertically on the bottom to keep harness organised. +12V for Dynamixel will be sent from backplane using 6 pins (1A each) and added GND next to each pin for proper return path. Need to add the Dynamixel connector to ESC PCB.
Cell Voltages will also be exposed in B to B connector, to connect it to monitoring IC on backplane, Need to add the balance JST on ESC PCB.
Thank You Ken for review of Pin Assignment Doc and catching my one MCU for two channels mistake. Each channel will have its own STM32G071C8T6 MCU.
For ESC MCU and FC MCU communication, two options - Either ESC MCU only runs AM32, FC takes care of everything else for ESC (No in-house firmware is needed for ESC) or ESC MCU controls Gate Driver IC and everything else on ESC and we send a custom packet from ESC MCU to FC and vice-versa with all data and configuration that is needed. (Will need in-house firmware for ESC on top of AM32 but will free up the FC). Need to discuss with firmware, upto them to decide.